Field
The present technology relates to fabrication of semiconductor devices.
Description of Related Art
The strong growth in demand for portable consumer electronics is driving the need for high-capacity storage devices. Non-volatile semiconductor memory devices, such as flash memory storage cards, are becoming widely used to meet the ever-growing demands on digital information storage and exchange. Their portability, versatility and rugged design, along with their high reliability and large capacity, have made such memory devices ideal for use in a wide variety of electronic devices, including for example digital cameras, digital music players, video game consoles, PDAs and cellular telephones.
Prior art FIGS. 1 and 2 respectively show a flowchart and schematic representation of steps in the production of semiconductor device memory cards. Given the large number of components which are assembled into a memory card, and the tremendous scale on which memory cards are produced within a semiconductor fabrication plant, it is important to provide a methodology for tracking semiconductor devices as they progress through the memory card production process. Manufacturing execution systems (MES) are known which receive information in real time from process tools and fab personnel to manage and, to an extent, track the production of memory cards. An MES maintains a database of the fabrication process which allows fab personnel to track semiconductor devices during the production process and also may be used to trace the source of problems should a defect be found in one or more assembled semiconductor devices. One example of a known MES platform is that from Camstar Inc. (owned by Siemens), Charlotte, N.C., USA. Camstar Inc. provides an MES platform under the name Camstar Manufacturing, and a quality management system under the name Camstar Quality. Other known platforms for managing the flow in a semiconductor memory card plant include Tango production monitoring suite by CyberDaemons Inc. of Hsinchu, Taiwan and an assembly line production (Cellmap) manager by Values First Consulting, Penang, Malaysia.
Referring to prior art FIGS. 1 and 2, memory die wafer lots 70 and controller die lot 72 are received in a memory card fabrication plant from wafer piece manufacturers. The wafers arrive with the integrated circuits defined thereon by the wafer piece manufacturers so that each memory die wafer piece includes a plurality of memory die, and each controller die wafer piece includes a plurality of controller die. In the embodiment shown in FIG. 2, a semiconductor device is being fabricated including a pair of memory die. Thus, two memory die wafer lots 70a and 70b are shown. It is also known to form semiconductor devices with one or more than two memory die. The wafer lot 70a used for the bottom memory die may be referred to as the wafer mother lot, while wafer lot(s) used for memory die above the bottom die may be referred to as the wafer sublots. Substrate lots 74 are also received in the memory card fabrication plant from a substrate manufacturer. The substrates in a substrate lot 74 may for example be a printed circuit board (PCB), leadframe or tape automated bonding (TAB) tape.
In order to prepare the wafer pieces in the wafer lots 70, 72 for affixation to a substrate in substrate lot 74, each wafer piece may have a protective tape applied to its active surface (the surface including the integrated circuits) and is then mounted to a chuck (not shown), active side down in step 20. Thereafter, a backgrind step 22 may be performed on the each wafer piece to thin the wafer down to a desired thickness. After backgrind step 22, the wafer pieces may be transferred to another tool where they are diced, for example by saw or laser, in step 24 so that they may be picked and placed onto the substrate.
In parallel with the die preparation steps, the substrate strips are received from the substrate strip manufacturer and processed. The strips are received in step 26. The strip manufacturer may mark individual substrates on the strip which were identified as bad substrates and unusable (such as substrates 204c shown with a “X” in FIG. 7). Individual substrates may also come from the strip manufacturer with an x-y location etched on the back of the substrate site. For example, in a 4×20 substrate strip, the substrates may be marked with A1 to A20, B1 to B20, C1 to C20 and D1 to D20. In step 28, the substrate strip may be laser marked with an ID. The laser marker also will scan the whole strip to identify the “X” out bad units.
In step 28, passive components may be mounted on the substrates of the strip in a surface mounting process. The solder paste may be applied in step 30. The passive components, also referred to herein as passives, may be mounted in step 32, and the solder may reflowed/cleaned in a step 34. The passives may include for example resistors and capacitors.
In step 42, the memory die and a controller die may be mounted on a substrate at a die attach tool 76. The tool 76 makes use of a known good die (KGD) map 78 which defines good and bad die for each wafer piece used. In particular, each die on each wafer piece in wafer lots 70, 72 may be operationally tested and given a rating such as 0,0 (flawless), A,A (good) or 1,1 (bad). The KGD map 78 is used by the die attach tool so that bad die on a wafer piece are ignored. In step 42, memory die and typically a controller die are mounted on a substrate to form a semiconductor device. As used herein, the term “device” refers to an assembly of a substrate, one or more semiconductor die on the substrate and, possibly, passive components on the substrate. The respective die, substrate and/or passives within a device may be referred to herein as “discrete components” of the semiconductor device.
Following the mounting of the die and passives on a substrate, the resulting device may then be wire bonded in step 48. The wire bonding step 48 is a time consuming process. As such, the device assembly lots may be split into a plurality of device assembly sublots so that wire bonding may be performed by a plurality of wire bonding tools 80 simultaneously (the number of wire bonding tools in FIG. 2 is by way of example only). In the wire bonding step 48, die bond pads on each of the die mounted to a substrate may be electrically coupled to contact pads on the substrate.
Following the wire bond step 48, the devices in the respective device assembly sublots may be encapsulated in a molding compound (step 50) in one or more tools 82, laser marked with an identifier (step 54) in one or more tools 84, and then singulated (step 56) in one or more tools 86. FIG. 2 shows the device assembly sublots remaining separated through each of these steps. However, one or more of the device assembly sublots may be reassembled into the device assembly lot following any of the steps 48 through 56.
The laser marking step 54 may be significant in that it allows information regarding a device assembly lot or sublot to be uploaded and tracked by the MES platform managing flow within the card fabrication plant. Prior art FIG. 3 shows an example of a conventional laser mark placed on the devices in a device assembly lot or sublot. The laser mark may include for example a logo and alphanumeric characters. The alphanumeric characters may include a plant code identifying the plant where the semiconductor device was made, a date code indicating when the semiconductor device was made, an MES lot or sublot number assigned to each device assembly lot or sublot, and a device ID code identifying the type of semiconductor package the device is. The information from the laser mark for a device assembly lot or sublot is assigned and stored by the MES, and used for device tracking and traceability.
Traditional MES platforms using this methodology have several limitations. First, the MES platform does not uniquely identify specific devices. At most, the MES assembly sublot number is unique to an entire device assembly sublot that went through a particular set of tools. Each particular device in such an MES assembly sublot will have the same identification code on its surface and be identified by the same identification code stored in the MES platform. Second, in part because of the generic marking of entire assembly sublots, there is no specific discrete component information directly associated with a specific device. That is, there is no direct link between a device's identification code and the semiconductor die, substrate and/or passive components used in that device.
As one consequence, when a problem with a device is detected during or after fabrication, conventional systems have limited ability find the source of the problem. When a problem with a device occurs, prior art systems may allow identification of an MES assembly sublot from which the problem device came. From the knowledge of the MES assembly sublot, it may be possible to determine what processes the problem device went through. From this, further research could reveal a specific wafer lot, and possibly reveal where a problem occurred. However, such research is time consuming and does not provide any specific identification or information on the discrete components from which the semiconductor device was formed.
Referring again to the flowchart and schematic representation of FIGS. 1 and 2, after singulation, semiconductor devices 90 may be inspected (step 60) and then put through one or more tests in step 62. These tests may include for example burn-in and memory read-write testing at high and low temperatures. Typically, semiconductor devices 90 from a number of device assembly lots are combined in the testing step. It is known to perform tests on 30,000 to 50,000 devices 90 from a plurality of device assembly lots. There is an N:1 consolidation of device assembly lots into a single device test lot, where N may for example be 25 device assembly lots.
The devices from respective assembly lots are reshuffled into different bins, depending on how the devices performed in the testing operations. In one example, it is known to divide the devices into seven bins (1-7), where devices classified in bins 1-4 have satisfactorily passed the testing operations and are passed on to a card test, described below. Devices classified in bins 5-7 failed the testing operation for one reason or another, and are subjected to a reclaim step 64 where they are retested. The reclaim operations will vary depending on whether a device was classified in bin 5, bin 6 or bin 7. A device may go through multiple reclaim processes. If, after one or more of these reclaim processes, a device is found to operate satisfactorily, it may be reclassified into one of bins 1-4 and passed on to the card test.
The card test in step 66 may be similar to the memory test in step 62, however content may be written to each device and its capabilities tested. Although not shown in FIG. 2, the card test may have a similar binning operation, where devices classified in certain bins are submitted for retest in a reclaim operation in step 68. Devices 90 which pass the card test may undergo some final inspection and processing steps (not shown) and then shipped.
In semiconductor memory card fabrication plants, the memory cards go through a number of distinct processes as indicated in FIG. 2, including in general the KGD (known good die) process, the card assembly process, the memory test process and the card/system test process. Given the consolidation and shuffling of devices 90 from the assembly process to the memory test process, and then again from the memory test process to the card/system test process, it is difficult and time consuming, if it is possible at all, to trace devices which are identified as problematic in the memory or card test phase using a conventional MES. This is in part due to the fact that memory devices are not marked with unique IDs, and thus, there is no record of how a specific semiconductor device performed in the testing operations.